The present invention relates to semiconductor memories including mask ROMs having short turn around time (TAT) and required to read data at high speed and also relates to system LSIs including semiconductor memories.
With recent increase in the degree of integration in LSI, system LSIs in each of which systems of electronic devices are incorporated into one LSI have been designed more actively. In such system LSIs, even memories such as a static random access memory (SRAM), a dynamic random access memory (DRAM) and a mask ROM as well as a microcomputer are integrated on one chip. Out of the semiconductor memories, the mask ROM is a nonvolatile read only memory into which data is written using a mask pattern in a fabrication process. Incorporation of this mask ROM into a system LSI requires not only high integration but also short TAT, high-speed accessibility, low power consumption and other features.
As a mask ROM having short TAT, a contact-programming mask ROM is widely used. The contact-programming mask ROM stores “1” or “0” data corresponding to the presence or absence of contact between a bit line and a metal oxide semiconductor field effect transistor (MOSFET) constituting a memory cell. In the contact-programming mask ROM, if a layer including a contact for determining programming is provided at an upper layer, the number of fabrication process steps after the programming can be reduced.
High integration of a mask ROM has been mainly achieved by miniaturization in a fabrication process to date. In the fabrication process for the miniaturized mask ROM, a shallow trench isolation (STI) is used to isolate a MOSFET. However, as the design rule decreases to 0.18 μm or less with the progress of miniaturization, a stress caused by the STI has a greater influence on an n-channel MOSFET (hereinafter, referred to as an nMOSFET). This problem was reported in IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 24-2-1 to 24-2-4.
FIG. 9 is a graph showing how a stress from an isolation insulating film affects a drive current of an nMOSFET. FIG. 10A is a top plan view showing a MOSFET isolated by an STI. FIG. 10B is a cross-sectional view of the MOSFET shown in FIG. 10A taken along line Xb—Xb. In FIG. 9, the abscissa represents the distance (finger length) from an end of the STI to the channel, and the ordinate represents a saturation current per a unit gate width.
As shown in FIGS. 10A and 10B, a general nMOSFET isolated by an STI includes: a gate insulating film 2008 provided on a semiconductor substrate 2007; a gate electrode 2001 provided on the gate insulating film 2008; sidewalls provided on both sides of the gate insulating film 2008 and the gate electrode 2001; source/drain regions 2002 containing an n-type impurity and defined in the semiconductor substrate 2007 below the both sides of the gate electrode 2001; and contacts 2003 respectively connected to the source/drain regions 2002. A channel 2005 is formed between the source/drain regions 2002 while the MOSFET is driven. The nMOSFET is electrically separated from an adjacent transistor by an STI 2004.
FIG. 9 shows that in such a general nMOSFET the saturation current is substantially constant when the finger length is Lsat or more but decreases sharply as the finger length becomes smaller than Lsat. The saturation current is at the minimum when the finger length is at the minimum (Lmin) determined according to the mask rule. In FIG. 9, the saturation current at the finger, length Lmin is 10% smaller than that at the finger length Lsat.
This change in the characteristics of the MOSFET occurs because thermal expansion of the STI 2004 shown in FIG. 10B in a fabrication process applies a stress 2006 to the channel 2005. In other words, the crystal structure of the channel 2005 is distorted by the stress, and this distortion affects the mobility of a carrier (electrons in the case of an nMOSFET). The stress from the STI is a physical stress, and the influence thereof on the mobility is greater as the distance between the STI 2004 and the channel 2005 is smaller.
By the influence of the stress, the drive current of an nMOSFET in the mask ROM decreases below a theoretical current value. Most of the time required of the mask ROM to read data is the time required of the nMOSFET in the memory cell for releasing the charge used for precharging a parasitic capacitance on a bit line. Accordingly, the decrease of the drive current flowing in the nMOSFET in the memory cell disadvantageously increases the time required of the whole mask ROM to read data.
FIG. 11A is a plan view showing a memory cell region of a semiconductor memory device having a conventional mask ROM. FIG. 11B is a cross-sectional view of the memory cell region of the conventional mask ROM taken along line XIb—XIb.
As shown in FIGS. 11A and 11B, the conventional mask ROM includes: a plurality of word lines 2101 extending in the row direction (lateral direction in FIG. 11A); and a plurality of bit lines 2101 crossing the word lines 2101 and extending in the column direction (vertical direction in FIG. 11A); and a plurality of MOSFETs whose gate electrodes 2104a are connected to the word lines 2101 and which are arranged in a matrix. Among the plurality of MOSFETs, the gate electrodes 2104a of those MOSFETs arranged in the same row are also part of a common gate line 2104. The gate line 2104 is connected to an associated one of the word lines 2101 via a gate contact 2107.
Each of the MOSFETs in the memory cells includes: the gate electrodes 2104a provided on a substrate with gate insulating films interposed therebetween; and source/drain regions (first and second doped layers) 2109 and 2110 formed in the substrate below the sides of the gate electrodes 2104a. The source regions of the MOSFETs arranged in the same row are united, and if the MOSFETs are nMOSFETs, the united source region is connected to a ground line 2103 via a source contact 2106.
As shown in FIG. 11B, an isolation insulating film 2111 is provided between every two adjacent MOSFETs arranged in the same column among the MOSFETs constituting the memory cells. The two adjacent MOSFETs sandwiched between two isolation insulating films share the same n-type doped region as their source regions.
In the conventional mask ROM, one memory cell 2108 is constituted by one nMOSFET. Each MOSFET stores “1” or “0” data corresponding to the presence or absence of connection between the drain region 2110 and the associated bit line 2102 via a drain contact 2105 and a via 2112.
Now, the principle of operation of the conventional mask ROM will be described.
FIG. 12A is an equivalent circuit diagram showing configurations of a memory cell region and a sense amplifier in the conventional mask ROM. FIG. 12B is timing charts showing operation waveforms of respective signals in the conventional mask ROM.
As shown in FIG. 12A, in the periphery of a memory cell region including a plurality of memory cells, a general mask ROM includes: an address decoder 2209 for activating a word line 2101 (see FIG. 11) selected based on address data; a sense amplifier 2203 connected to a bit line 2102 and used for amplifying a readout signal flowing on the bit line to logic levels and outputting a sense amplifier output signal Sout; and an output circuit 2207 for outputting the output from the sense amplifier 2203 to an external circuit.
In the example shown in FIG. 12A, word lines WL0, WL1, WL2, . . . out of the word lines 2101 are respectively connected to the gate electrodes of nMOSFETs 2201a, 2201b, 2201c, . . . out of the nMOSFETs 2201 whose sources are connected to the ground line. The nMOSFETs 2201a and 2201c are both connected to a bit line 2102 (bit line BL) through vias 2112. The nMOSFETs 2201b and 2201d are not connected to the bit line BL. The bit line BL is connected to the sense amplifier 2203 via a column selecting switch 2211 which is an nMOSFET turning ON or OFF according to a column selecting signal CA.
The sense amplifier 2203 includes: a NAND circuit 2213 having a first input port connected to the bit line BL via the column selecting switch 2211 and a second input port receiving the sense amplifier selecting signal SA; a first switch 2206 which is a pMOSFET whose source receives a power-supply voltage and whose drain is connected to the column selecting switch 2211 and the first input port of the NAND circuit 2213; and a second switch 2205 which is a pMOSFET whose source receives a power-supply voltage and whose drain is connected to the column selecting switch 2211 and the first input port of the NAND circuit 2213. The first switch 2206 is controlled with a precharge signal PC input to the gate electrode thereof. The gate electrode of the second switch 2205 is connected to an output port of the NAND circuit 2213.
Now, it will be described how the conventional mask ROM operates with reference to FIG. 12B. In FIG. 12B, the high-level voltages of the respective signals are 1.8 V.
First, the clock signal CK rises, and then the column selection signal CA and the precharge signal PC change to the high level and the low level, respectively. Then, the column selecting switch 2211 and the first switch 2206 turn ON, so that the bit line BL is precharged by the power-supply voltage. In this case, the column selecting signal CA changes to the high level only for the column selecting switch 2211 connected to the selected bit line, so that the unselected bit lines are not precharged. The bit lines are selected depending on the address of data to be read out. During a precharge period before the clock signal CK falls to the low level, the sense amplifier selecting signal SA and the column selecting signal CA are at the high level and the sense amplifier output signal Sout is at the low level. During this period, the output circuit 2207 inverts the output signal Sout to produce an output Out.
Next, the potential on the selected word line WL and the precharge signal PC rise to the high level by the falling edge of the clock signal CK. Then, the precharge period terminates, and the associated nMOSFETs 2201 constituting memory cells turn ON.
At this time, if a memory cell and the bit line BL are connected to each other through the via 2112, the bit line BL is discharged and the sense amplifier output signal Sout changes to the high level. Then, the output Out from the output circuit 2207 changes to the low level.
On the other hand, if the memory cell and the bit line BL is not connected to each other through the via 2112, the potential on the bit line 2102 does not change and the output Out remains at the high level as in the precharge period.
The period in which the clock signal CK falls, the sense amplifier output signal Sout changes to the high level and then the output Out from the output circuit 2207 changes from the high level to the low level will be hereinafter referred to as an “access period”.
In this manner, data “0” is stored if the nMOSFETs 2201 and the bit line BL are connected to each other through the vias 2112 (i.e., the output Out is at the low level), whereas data “1” is stored when the nMOSFET 2201 and the bit line BL are not connected to each other (the output Out is at the high level).
In the nMOSFETs 2201 connected to the bit line BL, leakage currents Ileak flow between drain and source even when low-level voltages are applied to the gate electrode thereof. The bit line BL is discharged by these leakage currents Ileak. This is because the conventional mask ROM includes the second switch 2205 within the sense amplifier 2203 in order to keep the potential on the bit line BL at the high level. The size of the second switch 2205 is determined such that the second switch 2205 allows the flow of a current larger than a leakage current Ileak_all that is the sum of the leakage currents flowing in the nMOSFETs 2201 connected to one bit line BL and smaller than the drive currents of the nMOSFETs 2201 when these nMOSFETs 2201 are ON.
In the aforementioned conventional mask ROM, with the reduction of the design rule, stresses from the trench insulating films 2111 provided in the memory cell region are applied to the nMOSFETs, causing a problem of reduction of the drive currents. A solution of the problem is to increase the drive currents of the memory cells.
In U.S. Pat. No. 5,959,877 and Japanese Laid-Open Publication No. 2000-195286, mask ROMs in which gates on word lines have branches were proposed. With this structure, a drive current for an MOSFET constituting a memory cell increases as compared to the conventional general mask ROM shown in FIG. 11.
In Japanese Laid-Open Publication No. 2003-017593, a semiconductor memory in which a ladder type gate is used and the drain of a memory cell is completely surrounded with the gate was disclosed. In this semiconductor memory, the drain of an MOSFET as a memory cell is not necessarily isolated by an STI, so that the current drive capability is not reduced by a stress on the channel caused by the STI. In addition, the drive current per one memory cell is more than three times as large as that in the conventional mask ROM, so that data is read out at higher speed.